DK-DEV-5SGXEA7N【PDF 232/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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8-12

Active Serial Configuration

SV51010

2014.01.10

Figure 8-4: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same

Data

Connect the resistor to a supply that

provides an acceptable input signal for the

FPGA device. V CCPGM must be high

enough to meet the VIH specification of

the I/O on the device and the external

host. Altera recommends powering up all

configuration system I/Os with V CCPGM .

For more information, refer to

the MSEL pin settings.

Memory

ADDR DATA[7..0]

V CCPGM V CCPGM

10 kΩ

10 kΩ

FPGA Device Master

MSEL[4..0]

CONF_DONE

FPGA Device Slave

MSEL[4..0]

CONF_DONE

External Host

(MAX II Device,

MAX V Device, or

Microprocessor)

GND

nSTATUS

nCE

DATA[]

nCONFIG

nCEO

N.C.

GND

nSTATUS

nCE

DATA[]

nCONFIG

nCEO

N.C.

You can leave the nCEO pin

unconnected or use it as a user

I/O pin when it does not feed

DCLK

DCLK

another device’s nCE pin.

Buffers

Connect the repeater buffers between the

FPGA master and slave device for DATA[]

and DCLK for every fourth device.

The nCE pins of the device in the chain are connected to GND, allowing configuration for these devices to

begin and end at the same time.

Active Serial Configuration

The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The

AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration

scheme, the Stratix V device controls the configuration interface.

Related Information

Stratix V Device Datasheet

Provides more information about the AS configuration timing.

DATA Clock (DCLK)

Stratix V devices generate the serial clock, DCLK , that provides timing to the serial interface. In the AS

configuration scheme, Stratix V devices drive control signals on the falling edge of DCLK and latch the

configuration data on the following falling edge of this clock pin.

The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS

multi-device configuration scheme. You can source DCLK using CLKUSR or the internal oscillator. If you use

the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options

dialog box, in the Configuration page of the Quartus II software.

After power-up, DCLK is driven by a 12.5 MHz internal oscillator by default. The Stratix V device determines

the clock source and frequency to use by reading the option bit in the programming file.

Altera Corporation

Configuration, Design Security, and Remote System Upgrades in Stratix V Devices

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